1. Field of the Invention
The present invention relates to a chip stack-type semiconductor package, and more particularly, to a chip stack-type semiconductor package and a method for fabricating the same, which has a high device packing density, a simple fabrication process owing to processing the packaging, not between semiconductor packages, but between chips, and excellent mechanical and electrical reliability owing to extremely short signal lines which are exposure protected.
2. Background of the Related Art
In general, a semiconductor device passes through an assembly process in which a wafer having integrated circuits formed thereon are separated into individual chips, and mounting the chips on a plastic or a ceramic package for easy mounting on a substrate. Thus, it may be said that main purposes of the semiconductor device packaging lie on securing a form for mounting on a substrate or socket and protection of functions of the semiconductor device. And, recently as a device packing density becomes the higher, technologies related to the assembly process, such as provision of multi-pin, micron assembly technology, and a variety of packages coming from development of a variety of mounting methods, and etc., are involved in great changes depending on sub-fields of the assembly process.
FIG. 1A illustrates a perspective view of a DIP(Dual Inline Package), and FIG. 1B illustrates a cross section showing an internal structure of the DIP in FIG 1A. An outline of semiconductor assembly process will be explained, taking a plastic DIP which is widely used currently as an example.
In the cutting of die wafer- having electric circuits formed thereon, in most of cases, since silicon is hard and brittle with a Moh's hardness of 7, a breaking force is exerted along a separation line having a material planted therein in advance in formation of the wafer for separating the wafer, to break and separate the wafer. And, the separated individual chips are bonded on a chip mounting region(die pad) 11 by Au--Si eutectoid method, soldering, or resin bonding, as necessary. The chip is bonded to the chip mounting region 11, not only for mounting on a substrate after assembly and, sometime in combination, as a terminal for electrical input/output or earthing, but also for dispersing a heat generated in operation of the device through the chip mounting region 11. After the chip 1 is bonded, the chip and an inner lead 12a of a lead frame is connected with gold wire, a conductive connection member 5, by bonding mostly using thermocompression or combination of thermocompression and ultrasonic sealing in case of a plastic sealing package using gold wire. After the chip 1 and the inner lead 12a are connected electrically by the wire bonding, molding is conducted in which the chip is enclosed in a high purity epoxy resin which is an important element that determines a- reliability of an integrated circuit, wherein improvements, such as provision of high purity resin and low stressed molding which can reduce stress to the integrated circuit, are under study. And, after the foregoing process is completed, an outer lead portion 12b is trimmed and formed to a required shape for mounting the IC package on a socket or a substrate, when the outer lead portion 12b is dipped in a plating or soldering solution for improvement of soldering effect.
In the meantime, the related art semiconductor packages are stacked when it is intended to increase a memory size, which requires very complicated process because the package units should be combined newly after the packaging is finished for fabrication of a chip stack-type package. That is, after individual packages are fabricated for individual chips by the packaging process, a process of stacking the completed individual packages should be conducted, that increases total fabrication processes and cost for fabricating the stack type semiconductor package. And, the related art stack type semiconductor package has difficulty in providing a lighter, thinner, shorter and smaller package, and a poor heat dissipation.